const spec t1 = {
	fpga_type       = "VHDL", 
	fpga_chip       = "3195APQ160-3",
	clock_pad       = "P160",
	not_error_pad   = "P55",
	finish_pad      = "P44",
	clock_divider   = "1",
	carry_weight    = "50",
	critical_weight = "100"
};

const spec uudat = {
	data = {"P0","P1","P3","P4"},
	txrdy = "pt",
	rxrdy = "pr"
};


//main(target = t1,chan (out) dataout : 8)

main(target = t1,port (out) pport = uudat:4)
{
	int x:8;
	x=0;
	do {
		x = x+1;
		pport !  x.(0..3);

	} while (1);
}