-- Handel Hardware Compiler Vn., C. Ian Page 1993
-- Modified Vhdl_out by M. Sauer
--   Output version of 29 Oct 1996
-- Written to <default.vhdl> on Fri Jan 30 19:51:42 2004
--
-- PROGRAM LISTING:
--
--    main (
--      chan (out) pport : 4)
--    {
--      {
--        int x : 8;
--        {
--          x = (0:8);
--          do 
--            {
--              x = (x + (1:8));
--              pport ! (x <- 4);
--            }
--          while (true);
--        }
--      }
--    }

--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity default is
--====================================
-- 元はC_pport_0 : out std_ulogic;等だけど、
-- outの信号を読み出したりするコードを吐くことが
-- あるので名前を変更して下で代入することにする
  port (
    signal def_C_pport_0 : out std_ulogic;
    signal def_C_pport_1 : out std_ulogic;
    signal def_C_pport_2 : out std_ulogic;
    signal def_C_pport_3 : out std_ulogic;
    signal def_C_pport_TXRDY : out std_ulogic;
    signal def_HCLK : in std_ulogic
--====================================
  );
end default;
architecture NETLIST of default is
    component LIBDFF
    	port ( 	Q : out std_ulogic;
    		CK,D : in std_ulogic
   );
 end component ; 
    component LIBOR2
    	port ( 	Y : out std_ulogic;
    		A,B : in std_ulogic
   );
 end component ; 
    component LIBXOR
    	port ( 	Y : out std_ulogic;
    		A,B : in std_ulogic
   );
 end component ; 
    component LIBAN2
    	port ( 	Y : out std_ulogic;
    		A,B : in std_ulogic
   );
 end component ; 
    component LIBINV
    	port ( 	Y : out std_ulogic;
    		A : in std_ulogic
   );
 end component ; 
    component LIBDFFR
    	port ( 	Q : out std_ulogic;
    		CK,RESETZ,D : in std_ulogic
   );
 end component ; 
--==================================
--=エラーになるしどうも使ってない模様
--=なのでコメントアウトした
--    component LIBLOG2
--    	port ( 	VDDLOG,GNDLOG : out std_ulogic;
--    		   );
-- end component ; 
--==================================

--=====================================
-- ここでentityのportにつながる信号を定義
    signal C_pport_0 : std_ulogic;
    signal C_pport_1 : std_ulogic;
    signal C_pport_2 : std_ulogic;
    signal C_pport_3 : std_ulogic;
    signal C_pport_TXRDY : std_ulogic;
    signal HCLK : std_ulogic;
--=====================================


    signal RZ_ES2_76 : std_ulogic;
    signal RZ_ES2_77 : std_ulogic;
    signal Opt_75 : std_ulogic;
    signal S_82 : std_ulogic;
    signal S_80 : std_ulogic;
    signal S_81 : std_ulogic;
    signal S_83 : std_ulogic;
    signal S_86 : std_ulogic;
    signal S_84 : std_ulogic;
    signal S_85 : std_ulogic;
    signal S_87 : std_ulogic;
    signal S_90 : std_ulogic;
    signal S_88 : std_ulogic;
    signal S_89 : std_ulogic;
    signal S_91 : std_ulogic;
    signal S_94 : std_ulogic;
    signal S_92 : std_ulogic;
    signal S_93 : std_ulogic;
    signal S_95 : std_ulogic;
    signal CE_x : std_ulogic;
    signal CY_23_28 : std_ulogic;
    signal CY_23_32 : std_ulogic;
    signal D_x_0 : std_ulogic;
    signal EX_22_0 : std_ulogic;
    signal D_x_1 : std_ulogic;
    signal EX_22_1 : std_ulogic;
    signal D_x_2 : std_ulogic;
    signal EX_22_2 : std_ulogic;
    signal D_x_3 : std_ulogic;
    signal EX_22_3 : std_ulogic;
    signal S_17 : std_ulogic;
    signal Q_x_0 : std_ulogic;
    signal Q_x_1 : std_ulogic;
    signal Q_x_2 : std_ulogic;
    signal Q_x_3 : std_ulogic;
    signal RZ_ES2_78 : std_ulogic;
    signal S_72 : std_ulogic;
    signal START : std_ulogic;
    signal RZ_ES2_79 : std_ulogic;
    signal S_73 : std_ulogic;

 -- >>SYSTEM SIGNALS<< 
signal VCC : std_ulogic ;
signal GND : std_ulogic ;
signal FINISH_OUT : std_ulogic ;
signal STOP_OUT : std_ulogic ;
begin
--====================================
-- ここでポートと結合
	def_C_pport_0 <= C_pport_0;
	def_C_pport_1 <= C_pport_1;
	def_C_pport_2 <= C_pport_2;
	def_C_pport_3 <= C_pport_3;
	def_C_pport_TXRDY <= C_pport_TXRDY;
	HCLK <= def_HCLK;
--====================================

--====================================
--=エラーになるし、あんまり意味なさそう
--=なのでコメントアウトしてみた
--CSupply :  port map (VDDLOG => VCC, GNDLOG => GND );
--====================================
    -- After fan-in adjustment     :   8 FFs,   15 gates,   2 inverters; size   23
    -- After netlist optimisations :   8 FFs,   15 gates,   2 inverters; size   23
    C0: LIBINV port map (Y => RZ_ES2_76,A => GND);
    C1: LIBDFFR port map (Q => C_pport_TXRDY,CK => HCLK,RESETZ => RZ_ES2_76,D => S_17);
    C2: LIBOR2 port map (Y => Opt_75,A => START,B => C_pport_TXRDY);
    C3: LIBINV port map (Y => RZ_ES2_77,A => GND);
    C4: LIBDFFR port map (Q => S_17,CK => HCLK,RESETZ => RZ_ES2_77,D => Opt_75);
    -- After compilation           :  15 FFs,   83 gates,   4 inverters; size  123
    -- Channel pport : 4 bits wide
    -- CPC_PortOut PROTOCOL CONVERTER
    -- CTRL: {  int x : 8;  {    x = (0:8);    do       {        x = (x + (1:8)); 
    -- Register x : 8 bits wide
    C6: LIBDFF port map (Q => Q_x_0,CK => HCLK,D => S_82);
    C7: LIBOR2 port map (Y => S_82,A => S_80,B => S_81);
    C8: LIBAN2 port map (Y => S_80,A => Q_x_0,B => S_83);
    C9: LIBAN2 port map (Y => S_81,A => D_x_0,B => CE_x);
    C10: LIBINV port map (Y => S_83,A => CE_x);
    C11: LIBINV port map (Y => EX_22_0,A => Q_x_0);
    C12: LIBDFF port map (Q => Q_x_1,CK => HCLK,D => S_86);
    C13: LIBOR2 port map (Y => S_86,A => S_84,B => S_85);
    C14: LIBAN2 port map (Y => S_84,A => Q_x_1,B => S_87);
    C15: LIBAN2 port map (Y => S_85,A => D_x_1,B => CE_x);
    C16: LIBINV port map (Y => S_87,A => CE_x);
    C17: LIBDFF port map (Q => Q_x_2,CK => HCLK,D => S_90);
    C18: LIBOR2 port map (Y => S_90,A => S_88,B => S_89);
    C19: LIBAN2 port map (Y => S_88,A => Q_x_2,B => S_91);
    C20: LIBAN2 port map (Y => S_89,A => D_x_2,B => CE_x);
    C21: LIBINV port map (Y => S_91,A => CE_x);
    C22: LIBDFF port map (Q => Q_x_3,CK => HCLK,D => S_94);
    C23: LIBOR2 port map (Y => S_94,A => S_92,B => S_93);
    C24: LIBAN2 port map (Y => S_92,A => Q_x_3,B => S_95);
    C25: LIBAN2 port map (Y => S_93,A => D_x_3,B => CE_x);
    C26: LIBINV port map (Y => S_95,A => CE_x);
    C27: LIBOR2 port map (Y => CE_x,A => START,B => S_17);
    -- CTRL: x = (0:8);
    -- Start: (426,429) = START
    -- (Part of) assignment: x = (0:8);
    -- Active_Expr: (428,429) = START
    -- CTRL: do   {    x = (x + (1:8));    pport ! (x <- 4);  }while (true);
    -- Control for UNTIL ~(true)
    -- Active_Expr: (480,481) = UN_FDBK_16
    -- Group of 1 INV gates
    -- 2-input decoder
    -- CTRL: {  x = (x + (1:8));  pport ! (x <- 4);}
    -- CTRL: x = (x + (1:8));
    -- Start: (439,446) = S_17
    -- (Part of) assignment: x = (x + (1:8));
    -- Active_Expr: (443,444) = S_17
    -- ADD1	EX_22_0	[Q_x_0, VCC]
    -- ADD1	EX_22_1	[Q_x_1, GND]
    C28: LIBAN2 port map (Y => CY_23_28,A => Q_x_0,B => Q_x_1);
    C29: LIBXOR port map (Y => EX_22_1,A => Q_x_1,B => Q_x_0);
    -- ADD1	EX_22_2	[Q_x_2, GND]
    C30: LIBAN2 port map (Y => CY_23_32,A => CY_23_28,B => Q_x_2);
    C31: LIBXOR port map (Y => EX_22_2,A => Q_x_2,B => CY_23_28);
    -- ADD1	EX_22_3	[Q_x_3, GND]
    C32: LIBXOR port map (Y => EX_22_3,A => Q_x_3,B => CY_23_32);
    -- ADD1	EX_22_4	[Q_x_4, GND]
    -- ADD1	EX_22_5	[Q_x_5, GND]
    -- ADD1	EX_22_6	[Q_x_6, GND]
    -- ADD1	EX_22_7	[Q_x_7, GND]
    C33: LIBAN2 port map (Y => D_x_0,A => EX_22_0,B => S_17);
    C34: LIBAN2 port map (Y => D_x_1,A => EX_22_1,B => S_17);
    C35: LIBAN2 port map (Y => D_x_2,A => EX_22_2,B => S_17);
    C36: LIBAN2 port map (Y => D_x_3,A => EX_22_3,B => S_17);
    -- CTRL: pport ! (x <- 4);
    -- Start: (450,467) = C_SEQ_0_21
    -- pport ! (x <- 4);
    -- Active_Expr: (459,460) = C_pport_TXRDY
    C37: LIBAN2 port map (Y => C_pport_0,A => Q_x_0,B => C_pport_TXRDY);
    C38: LIBAN2 port map (Y => C_pport_1,A => Q_x_1,B => C_pport_TXRDY);
    C39: LIBAN2 port map (Y => C_pport_2,A => Q_x_2,B => C_pport_TXRDY);
    C40: LIBAN2 port map (Y => C_pport_3,A => Q_x_3,B => C_pport_TXRDY);
    -- Start: (450,467) = C_pport_TXRDY
    -- 2-input decoder
    -- adding Clock Generator
    -- System hardware
    C41: LIBINV port map (Y => RZ_ES2_78,A => GND);
    C42: LIBDFFR port map (Q => S_72,CK => HCLK,RESETZ => RZ_ES2_78,D => VCC);
    C43: LIBINV port map (Y => S_73,A => S_72);
    C44: LIBINV port map (Y => RZ_ES2_79,A => GND);
    C45: LIBDFFR port map (Q => START,CK => HCLK,RESETZ => RZ_ES2_79,D => S_73);
    -- No Stop for Vhdl
    -- adding ClockConnections BlackBox for HClk
    -- adding ClockConnections for BufHClk
end NETLIST;