library IEEE;
use IEEE.STD_LOGIC_1164.all;

package hclibpackage is 
	component libor2
	    	port ( 	Y : out std_ulogic;
	    		A,B : in std_ulogic
		);
	end component;

	component LIBINV
		port ( 	Y : out std_ulogic;
			A : in std_ulogic
		);
	end component ;
	component LIBDFFR
		port ( 	Q : out std_ulogic;
			CK,RESETZ,D : in std_ulogic
		);
	end component ; 

	component LIBAN2
		port ( 	Y : out std_ulogic;
			A,B : in std_ulogic
		);
	end component ; 

	component LIBAN4
		port ( 	Y : out std_ulogic;
			A,B,C,D : in std_ulogic
		);
	end component ; 

	component LIBAN3
		port ( 	Y : out std_ulogic;
			A,B,C : in std_ulogic
		);
	end component ; 

	component libxor
	    	port ( 	Y : out std_ulogic;
	    		A,B : in std_ulogic
		);
	end component;

end;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity libor2 is
    	port ( 	Y : out std_ulogic;
    		A,B : in std_ulogic
   );
end libor2;

architecture arch_libor2 of libor2 is
begin
	Y <= A or B;
end arch_libor2;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity libinv is
    	port ( 	Y : out std_ulogic;
    		A : in std_ulogic
   );
end libinv;

architecture arch_libinv of libinv is
begin
	Y <= not(A);
end arch_libinv;


library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity libdffr is
	port ( 	Q : out std_ulogic;
		CK,RESETZ,D : in std_ulogic
	);
end libdffr;


architecture arch_libdffr of libdffr is
begin
	process(CK, RESETZ) begin
		if (RESETZ = '0') then
			Q <= '0';
		elsif (CK'event and CK='1') then
			Q <= D;
		end if;
	end process;
end arch_libdffr;


library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity liban2 is
    	port ( 	Y : out std_ulogic;
    		A,B : in std_ulogic
   );
end liban2;

architecture arch_liban2 of liban2 is
begin
	Y <= A and B;
end arch_liban2;


library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity libdff is
	port ( 	Q : out std_ulogic;
		CK,D : in std_ulogic
	);
end libdff;


architecture arch_libdff of libdff is
begin
	process(CK) begin
		if (CK'event and CK='1') then
			Q <= D;
		end if;
	end process;
end arch_libdff;


library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity liban4 is
    	port ( 	Y : out std_ulogic;
    		A,B,C,D : in std_ulogic
   );
end liban4;

architecture arch_liban4 of liban4 is
begin
	Y <= A and B and C and D;
end arch_liban4;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity liban3 is
    	port ( 	Y : out std_ulogic;
    		A,B,C : in std_ulogic
   );
end liban3;

architecture arch_liban3 of liban3 is
begin
	Y <= A and B and C;
end arch_liban3;


library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity libxor is
    	port ( 	Y : out std_ulogic;
    		A,B : in std_ulogic
   );
end libxor;

architecture arch_libxor of libxor is
begin
	Y <= A xor B;
end arch_libxor;